1. Field of the Invention
The invention relates generally to systems and methods for processing the surface of substrates, e.g., semiconductor wafers. In particular, the invention relates to such systems and methods that scan a beam along selected orientation angles to reduce substrate warpage and/or control substrate stresses and strains.
2. Description of Background Art
Microelectronic circuit and other microstructural features are created on a substrate through the use of photolithographic technology. Typically, photolithography tools and processes are designed to image substrates such as unstrained semiconductor wafers having a substantially or perfectly flat wafer surface topography. While unprocessed semiconductor wafers may be initially unstrained, subsequent wafer processing may warp or otherwise uncontrollably strain the wafers.
In general, warped substrates such as semiconductor wafers are accompanied with wasted tool operation time, increased wafer process costs, and reduced overall processing efficiency. For example, the robustness of the photolithographic process generally depends at least in part on the lithographic system's ability to achieve focus when the topography of the surface to be imaged deviates from an ideal. When the warping or the degree of non-flatness of the substrate surface exceeds the range of the depth of focus (DOF) of a system, a mask pattern imaged onto the photoresist layer on the substrate by the system will be out of focus in at least some regions on the substrate. This can result in flaws in the subsequent processing and lead to defective circuits or microstructures. One primary “flaw” of concern is achieving the desired critical dimension (CD) in terms of both size and shape of the feature. In short, excessive deviation of a substrate surface from the plane of focus of the photolithographic tools and processes represents a source of aberration from desired feature dimensions and resolution.
It is undesirable to use processes accompanied with unacceptable strain or warpage problems for other reasons as well. For example, the effectiveness of photolithographic processes for semiconductor wafers depends, often in part, on the alignment of a wafer under processing (or surface and/or interior features thereof) with respect to a mask used in the optical exposure of the photolithographic process. Misalignment of a wafer under processing with respect to the mask is undesirable and can occur when wafer strain is introduced in an uncontrolled manner. When misalignment exceeds the tolerance range, a resultant circuit may be rendered defective, thereby causing poor performance or even failure of the circuit. In short, uncontrolled stresses and strains accumulated over a series of wafer layers may result in alignment problems that result in the formation of defective microelectronic components such as transistors for either negative-channel or positive-channel metal-oxide-semiconductors (NMOS and PMOS).
Coherent and incoherent laser technologies may be used to carry out thermal processing semiconductor-based microelectronic devices such as processors, memories and other integrated circuits (ICs) that require thermal processes. For example, the source/drain parts of transistors may be formed by exposing regions of a silicon wafer substrate to electrostatically accelerated dopants containing boron, phosphorous or arsenic atoms. After implantation, the interstitial dopants are electrically inactive and require activation. Activation may be achieved by heating the entirety or a portion of the substrate to a particular processing temperature for a period of time sufficient for the crystal lattice to incorporate the impurity atoms into its structure. Typically, laser technologies are used to rapidly heat the wafer to temperatures near the semiconductor melting point to incorporate dopants at substitutional lattice sites, and the wafer is rapidly cooled to “freeze” the dopants in place.
A rapid thermal cycle is used to “activate” the dopant atoms in the junction areas to avoid any appreciable change in the dopant atom distribution. As a result, an ideal box-like activated dopant profile, as substantially defined by the implant process rather than by the subsequent heating, is created. Exemplary terminology used to describe laser-based thermal processing techniques include laser thermal processing (LTP), laser thermal annealing (LTA), and laser spike annealing (LSA). In some instances, these terms can be used interchangeably.
Laser processing techniques involving lasers and/or laser diodes typically involve forming a laser beam into a long, thin image, which in turn is quickly scanned across a surface to be heated, e.g., an upper surface of a semiconductor wafer. For example, LTP may use a continuous or pulsed, high-power, CO2 laser beam, which is coherent in nature. The CO2 laser beam is raster scanned over the wafer surface so all regions of the surface are exposed to at least one pass of the heating beam. Similarly, a laser diode bar may be used to produce an incoherent beam for scanning over the wafer surface.
In the time that it takes for the beam to pass over a particular location on the surface of the wafer, that location is raised to an annealing temperature. For example, raster scanning a 100-μm wide beam across a wafer surface at a constant velocity of 100 mm/s may result in a 1-millisecond dwell time for the heating cycle. A typical maximum temperature during this heating cycle might be about 1350° C. for silicon wafers. Within the dwell time needed to bring the wafer surface up to the maximum temperature, a layer only about 100 to about 200 micrometers below the surface region is heated. The bulk of the millimeter thick wafer serves to cool the surface almost as quickly as it was heated once the laser beam is past. Additional information regarding laser-based processing apparatuses and methods can be found in U.S. Pat. No. 6,747,245 and U.S. Patent Application Publication Nos. 2004/0188396, 2004/0173585, 2005/0067384, and 2005/0103998 each to Talwar et al.
Wafer warpage and strains are a well-known phenomenon in the art of semiconductor wafer processing. For example, implantation processes as described above tend to create stresses in semiconductor wafers. Similarly, temperature gradients associated with wafer surface heating also tends to induce stress in wafers. As observed in U.S. Pat. No. 6,865,308 to Conway et al., silicon wafers having layers deposited and annealed thereon at relatively high temperatures tend to become warped. In extreme cases, the wafer itself becomes so warped after a particular subprocess that the wafer cannot be properly secured to stepper chucks for subsequent subprocesses.
Laser-based semiconductor wafer processes, as discussed below, may result in undesirable strains and wafer warping. For example, laser spike annealing techniques has been extensively applied in current semiconductor industry for junction annealing to achieve excellent device performance. In the context of such applications, higher annealing temperatures are generally desirable because, as illustrated in FIG. 1, higher annealing temperatures tend to give rise to improved device performance. However, it has been observed that wafers processed using scanned laser beams tend to become warped. In some instances, the wafer warpage generated during LSA process may exceed the tight tolerance required for IC manufacturing processes such as those involving photolithography. In particular, FIG. 2 shows that wafer warpage generally increases with higher LSA temperature.
Nevertheless, strain associated with semiconductor substrates such as silicon wafers does not necessarily poses a problem in all semiconductor processing contexts. For example, strain engineering has been widely used recently to boost the transistor performance in silicon wafers. In particular, it has been observed that current flow may be improved by aligning strain with certain crystallographic and/or transistor orientations.
Thus, there is a need to find solutions to mitigate wafer warpage problems that may arise as a result of improved laser processing techniques that involve increased processing temperatures. In addition, there are opportunities in the art to employ laser processing techniques to produced improved microelectronic devices by providing a means to effect wafer strain in a controlled manner.